US 12,216,372 B2
Liquid crystal display device
Hajime Kimura, Kanagawa (JP); and Hideki Uochi, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Aug. 1, 2024, as Appl. No. 18/791,701.
Application 18/791,701 is a continuation of application No. 18/432,239, filed on Feb. 5, 2024.
Application 18/432,239 is a continuation of application No. 18/112,536, filed on Feb. 22, 2023, granted, now 11,899,329, issued on Feb. 13, 2024.
Application 18/112,536 is a continuation of application No. 17/462,035, filed on Aug. 31, 2021, granted, now 11,592,719, issued on Feb. 28, 2023.
Application 17/462,035 is a continuation of application No. 16/735,819, filed on Jan. 7, 2020, granted, now 11,126,053, issued on Sep. 21, 2021.
Application 16/735,819 is a continuation of application No. 16/435,609, filed on Jun. 10, 2019, granted, now 10,539,847, issued on Jan. 21, 2020.
Application 16/435,609 is a continuation of application No. 15/998,993, filed on Aug. 20, 2018, granted, now 10,324,347, issued on Jun. 18, 2019.
Application 15/998,993 is a continuation of application No. 15/899,409, filed on Feb. 20, 2018, granted, now 10,054,830, issued on Aug. 21, 2018.
Application 15/899,409 is a continuation of application No. 15/397,813, filed on Jan. 4, 2017, granted, now 9,904,127, issued on Feb. 27, 2018.
Application 15/397,813 is a continuation of application No. 15/068,801, filed on Mar. 14, 2016, granted, now 9,823,526, issued on Nov. 21, 2017.
Application 15/068,801 is a continuation of application No. 14/140,005, filed on Dec. 24, 2013, granted, now 9,316,881, issued on Apr. 19, 2016.
Application 14/140,005 is a continuation of application No. 13/442,932, filed on Apr. 10, 2012, granted, now 8,619,227, issued on Dec. 31, 2013.
Application 13/442,932 is a continuation of application No. 13/015,991, filed on Jan. 28, 2011, granted, now 8,164,729, issued on Apr. 24, 2012.
Application 13/015,991 is a continuation of application No. 12/848,247, filed on Aug. 2, 2010, granted, now 7,880,848, issued on Feb. 1, 2011.
Application 12/848,247 is a continuation of application No. 11/566,005, filed on Dec. 1, 2006, granted, now 7,773,182, issued on Aug. 10, 2010.
Claims priority of application No. 2005-350147 (JP), filed on Dec. 5, 2005.
Prior Publication US 2024/0393651 A1, Nov. 28, 2024
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1368 (2013.01) [G02F 1/133345 (2013.01); G02F 1/133371 (2013.01); G02F 1/133555 (2013.01); G02F 1/134363 (2013.01); G02F 1/13439 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G02F 1/133553 (2013.01); G02F 1/134372 (2021.01); G02F 1/136209 (2013.01); G02F 1/136222 (2021.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); G02F 2201/124 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A liquid crystal display device having a liquid crystal layer provided over a pixel electrode and a common electrode comprising:
a semiconductor layer electrically connected to the pixel electrode and having a channel formation region of a transistor;
a gate line over the semiconductor layer;
a first insulating layer over the gate line;
a source line over the first insulating layer and electrically connected to the semiconductor layer;
a first conductive layer over the first insulating layer and electrically connected to the semiconductor layer and the pixel electrode; and
a common wiring over the first insulating layer and electrically connected to the common electrode,
wherein the first conductive layer has a same material as the source line,
wherein the semiconductor layer comprises silicon,
wherein each of the pixel electrode and the common electrode comprises indium tin oxide,
wherein the common electrode is in contact with an upper surface of the common wiring,
wherein in a plan view, the common wiring is disposed on a side of another adjacent pixel in a direction intersecting a direction in which the common wiring extends, and does not overlap with the first conductive layer,
wherein in a plan view, the channel formation region of the transistor does not overlap with the common electrode,
wherein in a plan view, the pixel electrode has a comb-shape,
wherein in a plan view, the common electrode has an opening,
wherein the opening of the common electrode has a first region overlapping with the pixel electrode and a second region not overlapping with the pixel electrode, and
wherein the common wiring overlaps with the second region.