a first substrate;

a plurality of gate lines disposed on the first substrate and extending in a first direction, and a plurality of data lines disposed on the first substrate and extending in a second direction; the first direction intersecting the second direction, and the plurality of the gate lines and the plurality of data lines defining a plurality of sub-pixel regions;

a plurality of thin film transistors disposed on the first substrate; a thin film transistor being located in a sub-pixel region; and

a plurality of reflective electrodes disposed on a side of the plurality of thin film transistors away from the first substrate; a reflective electrode being located in the sub-pixel region, and the reflective electrode being electrically connected to the thin film transistor located in the same sub-pixel region as the reflective electrode, wherein

each reflective electrode has a border including: a plurality of first sub-borders extending in the first direction, a plurality of second sub-borders extending in the second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; an intersection of extension lines of the first sub-border and the second sub-border that are adjacent is located outside the border of the reflective electrode;

the array substrate further includes:

a plurality of first electrodes with a same material and disposed in a same layer as the plurality of gate lines, and a first electrode being located in the sub-pixel region; and

a plurality of second electrodes with a same material and disposed in a same layer as the plurality of data lines, and a second electrode being located in the sub-pixel region, wherein

the first electrode and the second electrode that are located in the same sub-pixel region constitute a storage capacitor;

a minimum spacing between a border of an orthogonal projection of the second electrode on the first substrate and a border of an orthogonal projection of a data line adjacent to the second electrode on the first substrate is a first preset value;

each thin film transistor includes a source and a drain;

in a case where the second electrode is electrically connected to a source of the thin film transistor located in the same sub-pixel region as the second electrode, a spacing, in the first direction, between the border of the orthogonal projection of the second electrode on the first substrate and a border of an orthogonal projection of a drain of the thin film transistor located in the same sub-pixel region as the second electrode on the first substrate is a second preset value, and the second preset value is greater than or equal to the first preset value; and

in a case where the second electrode is electrically connected to the drain of the thin film transistor located in the same sub-pixel region as the second electrode, a spacing, in the first direction, between the border of the orthogonal projection of the second electrode on the first substrate and a border of an orthogonal projection of the source of the thin film transistor located in the same sub-pixel region as the second electrode on the first substrate is a third preset value, and the third preset value is greater than or equal to the first preset value.