US 12,216,226 B2
Radar system
Ulrich Moehlmann, Moisburg (DE); Cristian Pavao Moreira, Frouzins (FR); and Andreas Johannes Köllmann, Rosengarten (DE)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on May 4, 2022, as Appl. No. 17/661,944.
Claims priority of application No. 21305628 (EP), filed on May 12, 2021.
Prior Publication US 2022/0365173 A1, Nov. 17, 2022
Int. Cl. G01S 7/40 (2006.01); G01S 13/02 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01); H03K 19/20 (2006.01)
CPC G01S 7/40 (2013.01) [G01S 7/4017 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01); G01S 2013/0254 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising:
a phase comparator connected to receive the first clock signal and a feedback signal;
a loop filter connected to receive an output signal from the phase comparator;
a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency;
a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency;
a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and
a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal;
wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and
wherein the divide by n clock divider comprises five flip-flops, FFs, arranged to receive the second clock signal from the second oscillator, three OR gates and one AND gate arranged to receive outputs from the FFs.