| CPC G01R 31/318536 (2013.01) [G01R 31/318544 (2013.01)] | 20 Claims |
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1. An apparatus comprising:
a plurality of circuit blocks;
a plurality of scan-enabled flip-flop circuits, coupled in a sequential manner across the plurality of circuit blocks, configured to shift a scan chain test signal from a test input interface to a test output interface; and
a plurality of scan signature circuits, coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and configured to:
in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits; and
wherein the plurality of scan-enabled flip-flop circuits is further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.
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