US 12,216,160 B2
Clock shaper circuit for transition fault testing
Wilson Pradeep, Bangalore (IN); Sriraj Chellappan, Bangalore (IN); and Shruti Gupta, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Mar. 13, 2023, as Appl. No. 18/182,848.
Application 18/182,848 is a continuation of application No. 17/566,190, filed on Dec. 30, 2021, granted, now 11,604,221.
Prior Publication US 2023/0243887 A1, Aug. 3, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G11C 19/28 (2006.01); H03K 19/20 (2006.01)
CPC G01R 31/31727 (2013.01) [G01R 31/3177 (2013.01); G11C 19/287 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a clock shaper circuit, comprising:
a synchronizing circuit configured to provide a synchronizing signal based on a scan enable signal;
a clock leaker circuit coupled to the synchronizing circuit configured to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and
selection circuitry coupled to the clock leaker circuit configured to receive the second clock signal and select between a shift clock and the second clock signal based on the synchronizing signal.