US 12,216,157 B2
Package structure and testing method
Chen-Chao Wang, Kaohsiung (TW); Tsung-Tang Tsai, Kaohsiung (TW); and Chih-Yi Huang, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Aug. 22, 2023, as Appl. No. 18/236,930.
Application 18/236,930 is a continuation of application No. 16/812,232, filed on Mar. 6, 2020, granted, now 11,733,294.
Prior Publication US 2023/0393194 A1, Dec. 7, 2023
Int. Cl. H01L 23/498 (2006.01); G01R 31/28 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/552 (2006.01); H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01)
CPC G01R 31/2896 (2013.01) [H01L 23/49822 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/3192 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a wiring structure including at least one conductive circuit layer and a test circuit structure disposed adjacent to an interconnection portion of the at least one conductive circuit layer;
a first electronic device electrically connected to the wiring structure; and
a second electronic device electrically connected to the wiring structure,
wherein the test circuit structure is not electrically connected to the interconnection portion of the at least one conductive circuit layer.