US 12,216,153 B2
Semiconductor product with edge integrity detection structure
Xiaoming Li, Newport Beach, CA (US); Liming Tsau, Irvine, CA (US); and Andy Brotman, Irvine, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Mar. 21, 2022, as Appl. No. 17/700,186.
Prior Publication US 2023/0296664 A1, Sep. 21, 2023
Int. Cl. G01R 31/28 (2006.01); H01L 23/58 (2006.01)
CPC G01R 31/2858 (2013.01) [G01R 31/2896 (2013.01); H01L 23/585 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor product, comprising:
a semiconductor chip;
an edge integrity detection structure extending along at least part of an edge of the semiconductor chip,
the edge integrity detection structure comprising a stack of conductive layers, wherein the stack has first lateral side and a second lateral side opposite the first lateral side,
wherein a first layer of the conductive layers extends from a first end of the first layer associated with the first lateral side to a second end of the first layer associated with the second lateral side and is coupled to a second layer of the stack by a first vertical connection element at the first end of the first layer of the stack,
wherein the second layer extends from a first end of the second layer associated with the first lateral side to a second end of the second layer associated with the second lateral side,
wherein a third layer of the conductive layers extends from a first end of the third layer associated with the first lateral side to a second end of the third layer associated with the second lateral side and is coupled to the second layer of the stack by a second vertical connection element at the second end of the third layer of the stack,
wherein a fourth layer of the conductive layers extends from a first end of the fourth layer associated with the first lateral side to a second end of the fourth layer associated with the second lateral side and is coupled to the third layer of the stack by a third vertical connection element at the first end of the fourth layer of the stack,
wherein the second layer is not coupled to the third layer at the first end of the third layer,
wherein the first end of the first layer is opposite the second end of the first layer, the first end of the second layer is opposite the second end of the second layer, the first end of the third layer is opposite the second end of the third layer and the first end of the fourth layer is opposite the second end of the fourth layer; and
circuitry formed in and/or on the semiconductor chip, being electrically connected with the edge integrity detection structure, and being configured to evaluate an electric characteristic of the edge integrity detection structure to provide a signal indicative of an integrity status of the edge.