| CPC B81B 3/0013 (2013.01) [B81C 1/00968 (2013.01); B81B 2203/0109 (2013.01); B81B 2203/04 (2013.01); B81B 2207/012 (2013.01); B81B 2207/03 (2013.01); B81B 2207/07 (2013.01)] | 20 Claims |

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1. An integrated chip (IC), comprising:
a microelectromechanical system (MEMS) comprising:
an interconnect structure in a dielectric structure, which overlies a semiconductor substrate;
an additional semiconductor substrate overlying the dielectric structure and comprising a movable mass spaced from the semiconductor substrate;
a cavity between the semiconductor substrate and the movable mass, wherein opposite sidewalls of the movable mass are between opposite sidewalls of the cavity; and
a first piezoelectric anti-stiction structure on a first surface of the cavity, wherein the first piezoelectric anti-stiction structure comprises a first piezoelectric structure and a first electrode; and
bias circuitry electrically coupled to the first electrode, wherein the bias circuitry is configured to provide a first voltage to the first electrode;
wherein the interconnect structure has a pair of vias extending from a first elevation at a bottom surface of the cavity to a second elevation at a bottom surface of the additional semiconductor substrate, and wherein the pair of vias have different heights and are electrically coupled respectively to the movable mass and the first piezoelectric anti-stiction structure.
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