US 12,214,672 B2
Short circuit protection system for battery packs
Murat Kubilay Ozguc, Istanbul (TR); and Derya Ahmet Kocabas, Istanbul (TR)
Assigned to ISTANBUL TEKNIK UNIVERSITESI, Istanbul (TR)
Appl. No. 18/019,246
Filed by ISTANBUL TEKNIK UNIVERSITESI, Istanbul (TR)
PCT Filed May 9, 2022, PCT No. PCT/TR2022/050405
§ 371(c)(1), (2) Date Feb. 2, 2023,
PCT Pub. No. WO2022/265597, PCT Pub. Date Dec. 22, 2022.
Claims priority of application No. 2021/009693 (TR), filed on Jun. 14, 2021.
Prior Publication US 2023/0286384 A1, Sep. 14, 2023
Int. Cl. B60L 3/00 (2019.01); B60L 3/04 (2006.01); H02H 7/18 (2006.01)
CPC B60L 3/0046 (2013.01) [H02H 7/18 (2013.01); B60L 3/04 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A short circuit protection system preferably for high voltage battery packs which is semiconductor based and provides protection with a faster response time, comprising:
at least one desaturation circuit comprising at least one resistor, at least one capacitor, and at least one diode,
at least one MOSFET connected with the desaturation circuit,
at least one driver for driving the MOSFET,
at least one gate resistor, wherein one end of the at least one gate resistor is connected with the driver and the other end of the at least one gate resistor is connected with the MOSFET,
at least one amplifier circuit configured to amplify the voltage signal passing through the gate resistor,
at least one integral circuit connected with the output of the amplifier circuit and is configured to integrate the current measured from the gate resistor to find the load value of the gate resistor,
at least one gate comparison circuit, wherein one input of the at least one gate comparison circuit is connected with the gate resistor for measuring the voltage passing through the gate resistor and the other input of the at least one gate comparison circuit is connected with the integral circuit for measuring the load on the gate resistor and comparing the voltage and load values,
at least one comparison circuit, wherein one input of the at least one comparison circuit is connected with the desaturation circuit and the other input of the at least one comparison circuit is connected with the gate comparison circuit and is configured to compare error signals from the desaturation and gate comparison circuits and generate a result signal.