US 12,213,548 B2
Hybrid memory module
Frederick A. Ware, Los Altos Hills, CA (US); John Eric Linstadt, Palo Alto, CA (US); and Kenneth L. Wright, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/852,266.
Application 17/852,266 is a continuation of application No. 17/089,899, filed on Nov. 5, 2020, granted, now 11,456,025.
Application 17/089,899 is a continuation of application No. 16/344,321, granted, now 10,847,196, issued on Nov. 24, 2020, previously published as PCT/US2017/055908, filed on Oct. 10, 2017.
Claims priority of provisional application 62/415,143, filed on Oct. 31, 2016.
Prior Publication US 2022/0406354 A1, Dec. 22, 2022
Int. Cl. G06F 12/02 (2006.01); A41D 3/04 (2006.01); A45F 3/04 (2006.01); G06F 12/0804 (2016.01); G06F 12/084 (2016.01); G06F 12/0895 (2016.01); G11C 5/04 (2006.01); G11C 11/00 (2006.01); G11C 14/00 (2006.01); A45F 3/00 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01)
CPC A41D 3/04 (2013.01) [A45F 3/04 (2013.01); G06F 12/0246 (2013.01); G06F 12/0804 (2013.01); G06F 12/084 (2013.01); G06F 12/0895 (2013.01); G11C 5/04 (2013.01); G11C 11/005 (2013.01); G11C 14/0018 (2013.01); A45F 2003/001 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/305 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7205 (2013.01); G11C 7/22 (2013.01); G11C 11/4076 (2013.01); G11C 2207/2245 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A method of caching data from a non-volatile memory, the method comprising:
maintaining non-volatile cache lines of the data in the non-volatile memory;
maintaining a tag cache and a direct cache across volatile memory dies, the direct cache including direct cache lines each distributed across the volatile memory dies;
receiving a read command directed to one of the non-volatile cache lines in the non-volatile memory;
reading from the tag cache to determine whether the one of the non-volatile cache lines in the non-volatile memory has a corresponding data entry in the cache memory; and
if the one of the non-volatile cache lines in the non-volatile memory lacks the corresponding data entry, copying the data from the one of the non-volatile cache lines in the non-volatile memory to one of the direct cache lines distributed across the volatile memory dies.