US 11,889,769 B2
Memory cell with top electrode via
Ming-Che Ku, Hsinchu (TW); Harry-Hak-Lay Chuang, Zhubei (TW); Hung Cho Wang, Taipei (TW); Tsun Chung Tu, Tainan (TW); Jiunyu Tsai, Hsinchu (TW); and Sheng-Huang Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/872,520.
Application 17/009,905 is a division of application No. 16/416,555, filed on May 20, 2019, granted, now 10,790,439, issued on Sep. 29, 2020.
Application 17/872,520 is a continuation of application No. 17/009,905, filed on Sep. 2, 2020, granted, now 11,489,107.
Claims priority of provisional application 62/702,581, filed on Jul. 24, 2018.
Prior Publication US 2022/0359815 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/80 (2023.01); H01F 10/32 (2006.01); H01F 41/34 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); G11C 11/16 (2006.01)
CPC H10N 50/80 (2023.02) [H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); G11C 11/161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate, wherein the top electrode has a width that decreases as a height of the top electrode increases;
a bottom electrode via coupling the bottom electrode to a lower interconnect; and
an upper interconnect structure coupled to the top electrode, wherein the upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode, wherein the vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.
 
7. An integrated chip, comprising:
a magnetic tunnel junction stack surrounded by a dielectric structure disposed over a substrate, wherein the magnetic tunnel junction stack comprises a free layer and a fixed layer disposed between a bottom electrode and a top electrode; and
an interconnection disposed on the top electrode, wherein the interconnection has a vertically extending surface that is disposed laterally between a first outermost sidewall and a second outermost sidewall of the interconnection, the vertically extending surface extending below a top of the top electrode.
 
16. An integrated chip, comprising:
a memory device surrounded by a dielectric structure disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode;
a bottom electrode via coupling the bottom electrode to a lower interconnect;
an upper interconnect structure on the top electrode, wherein the upper interconnect structure has both a first outermost sidewall and an interior sidewall disposed along a first side of the top electrode; and
wherein the interior sidewall faces the top electrode and has a smaller height than the first outermost sidewall.