US 11,889,726 B2
Display device
Han Sung Bae, Seongnam-si (KR); Se Ho Kim, Cheonan-si (KR); Sun Ja Kwon, Gunpo-si (KR); Dong Wook Kim, Anyang-si (KR); Jun Yong An, Anyang-si (KR); Sang Moo Choi, Yongin-si (KR); and Jun Won Choi, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Dec. 31, 2020, as Appl. No. 17/139,919.
Application 17/139,919 is a continuation of application No. 16/780,729, filed on Feb. 3, 2020, granted, now 10,886,358.
Application 16/780,729 is a continuation of application No. 16/175,753, filed on Oct. 30, 2018, granted, now 10,553,667, issued on Feb. 4, 2020.
Claims priority of application No. 10-2017-0171373 (KR), filed on Dec. 13, 2017.
Prior Publication US 2021/0126084 A1, Apr. 29, 2021
Int. Cl. H01L 27/32 (2006.01); H10K 59/131 (2023.01); G09G 3/3225 (2016.01); G09G 3/3233 (2016.01); H01L 27/12 (2006.01); H10K 59/121 (2023.01); H10K 77/10 (2023.01); G09G 3/3266 (2016.01)
CPC H10K 59/131 (2023.02) [G09G 3/3225 (2013.01); G09G 3/3233 (2013.01); H01L 27/1244 (2013.01); H10K 59/1213 (2023.02); H10K 77/111 (2023.02); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0297 (2013.01); H01L 27/1214 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display device, comprising:
a display area including a pixel circuit comprising a pixel transistor, a scan line connected to a gate electrode of the pixel transistor, and a data line connected to a first electrode of the pixel transistor; and
a non-display area adjacent to the display area, the non-display area including a demultiplexing circuit unit and a scan transmission line connected to the scan line and overlapping with the demultiplexing circuit unit,
wherein the demultiplexing circuit unit comprises a demultiplexer transistor including a demultiplexer gate electrode in a same layer as the gate electrode of the pixel transistor, a data input electrode and a data output electrode in a same layer as the first electrode of the pixel transistor, and
wherein the scan transmission line is located in a different conductive layer from the pixel transistor and the demultiplexer transistor.