US 11,889,705 B2
Interconnect landing method for RRAM technology
Hsia-Wei Chen, Taipei (TW); Chih-Yang Chang, Yuanlin Township (TW); Chin-Chieh Yang, New Taipei (TW); Jen-Sheng Yang, Keelung (TW); Kuo-Chi Tu, Hsin-Chu (TW); Wen-Ting Chu, Kaohsiung (TW); and Yu-Wen Liao, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 3, 2021, as Appl. No. 17/392,555.
Application 16/578,356 is a division of application No. 16/108,594, filed on Aug. 22, 2018, granted, now 10,566,387, issued on Feb. 18, 2020.
Application 16/108,594 is a division of application No. 15/442,174, filed on Feb. 24, 2017, granted, now 10,163,981, issued on Dec. 25, 2018.
Application 17/392,555 is a continuation of application No. 16/695,537, filed on Nov. 26, 2019, granted, now 11,094,744.
Application 16/695,537 is a continuation of application No. 16/578,356, filed on Sep. 22, 2019, granted, now 10,903,274, issued on Jan. 26, 2021.
Claims priority of provisional application 62/328,215, filed on Apr. 27, 2016.
Prior Publication US 2021/0366988 A1, Nov. 25, 2021
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 63/00 (2023.01); H10B 10/10 (2023.01); H10B 99/00 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/80 (2023.02) [H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H10B 10/10 (2023.02); H10B 63/30 (2023.02); H10B 99/00 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/826 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
a memory device disposed over the first interconnect and surrounded by a second ILD layer;
sidewall spacers arranged along opposing sides of the memory device;
an etch stop layer arranged on the sidewall spacers, wherein a top portion of each of the sidewall spacers has an upper surface leveled with an upper surface of the memory device; and
a second interconnect extending from a top of the second ILD layer to the upper surfaces of the memory device, the sidewall spacers, and the etch stop layer, wherein a portion of each of the sidewall spacers adjacent to the top portion of this sidewall spacer is in direct contact with the second interconnect.