US 11,889,695 B2
Device, a method used in forming a circuit structure, a method used in forming an array of elevationally-extending transistors and a circuit structure adjacent thereto
Paolo Tessariol, Arcore (IT); Justin B. Dorhout, Boise, ID (US); Indra V. Chary, Boise, ID (US); Jun Fang, Boise, ID (US); Matthew Park, Boise, ID (US); Zhiqiang Xie, Meridian, ID (US); Scott D. Stull, Boise, ID (US); Daniel Osterberg, Boise, ID (US); Jason Reece, Boise, ID (US); and Jian Li, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 18, 2021, as Appl. No. 17/504,313.
Application 17/504,313 is a division of application No. 15/705,179, filed on Sep. 14, 2017, granted, now 11,177,271.
Prior Publication US 2022/0037360 A1, Feb. 3, 2022
Int. Cl. H01L 27/11582 (2017.01); H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 43/50 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/02636 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 29/1037 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/50 (2023.02); H10B 43/10 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A device comprising:
an array of elevationally-extending transistors; and
a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising:
a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material;
operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and which individually electrically couple to an electronic component below the vertically-alternating tiers; and
dummy structures individually extending elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers, the operative conductive vias and the dummy structures individually comprising a conductive core and an insulative periphery.