US 11,889,694 B2
Three-dimensional memory device with separated contact regions and methods for forming the same
Hardwell Chibvongodze, Hiratsuka (JP); Zhixin Cui, Nagoya (JP); Rajdeep Gautam, Nagoya (JP); and Hiroyuki Ogawa, Nagoya (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Aug. 9, 2021, as Appl. No. 17/397,846.
Prior Publication US 2023/0041950 A1, Feb. 9, 2023
Int. Cl. G11C 11/34 (2006.01); H10B 43/27 (2023.01); G11C 5/06 (2006.01); H01L 23/522 (2006.01); G11C 8/14 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 5/063 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising a memory die, wherein the memory die comprises:
an alternating stack of insulating layers and electrically conductive layers overlying a substrate and laterally extending through a series of regions that comprises, in a spatial order along a first horizontal direction, a first contact region, a first memory array region, an auxiliary contact region, a second memory array region, and a second contact region;
arrays of memory openings located in the first memory array region and the second memory array region; and
arrays of memory opening fill structures located within the arrays of memory openings and comprising a respective vertical stack of memory elements, wherein:
the alternating stack of insulating layers and electrically conductive layers comprises a lower layer stack including a first subset of the insulating layers and a first subset of the electrically conductive layers located underneath a horizontal plane, and an upper layer stack including a second subset of the insulating layers and a second subset of the electrically conductive layers located above the horizontal plane;
the first contact region and the second contact region comprise first contact via structures contacting a respective electrically conductive layer of the first subset of the electrically conductive layers; and
the auxiliary staircase region comprises second contact via structures contacting a respective electrically conductive layer of the second subset of the electrically conductive layers.