| CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H01L 27/0688 (2013.01); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)] | 20 Claims |
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1. A vertical memory device, comprising:
a substrate;
a plurality of channels extending in a vertical direction with respect to a top surface of the substrate;
a plurality of gate lines surrounding a predetermined number of channels from among the channels, wherein the gate lines are arranged and spaced apart from one another along the vertical direction, and the gate lines comprise a ground selection line (GSL), a plurality of word lines, and a string selection line (SSL) sequentially stacked on the top surface of the substrate;
a plurality of common wirings electrically connected to the gate lines, wherein a first one of the common wirings is electrically connected to the SSL, a second one of the common wirings is electrically connected to the GSL, and remaining ones of the common wirings other than the first and second common wirings are electrically connected to the word lines,
wherein the first one of the common wirings, the second one of the common wirings, and the remaining ones of the common wirings are disposed at a same level and are respectively connected to the SSL, the GSL, and the word lines via a plurality of contacts,
wherein the gate lines extend in a first direction, and the common wirings extend in a second direction crossing the first direction,
wherein a length of the first one of the common wirings, a length of the second one of the common wirings, and lengths of the remaining ones of the common wirings are about equal to each other in the second direction; and
a plurality of signal wirings electrically connected to the gate lines via the common wirings, wherein the signal wirings are distributed at a plurality of levels.
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