CPC H10B 12/50 (2023.02) [H10B 12/0335 (2023.02); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02)] | 20 Claims |
1. A semiconductor memory device, comprising:
a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells;
a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction; and
a plurality of dummy active regions in the dummy cell region, each of the plurality of dummy active regions extending in the long axis direction, each of the plurality of dummy active regions having a second maximum width greater than a first maximum width in the short axis direction.
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