US 11,889,677 B2
Method for forming capacitor holes
Xifei Bao, Hefei (CN); and Jinguo Fang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 18, 2021, as Appl. No. 17/455,474.
Application 17/455,474 is a continuation of application No. PCT/CN2021/092283, filed on May 8, 2021.
Claims priority of application No. 202010454225.X (CN), filed on May 26, 2020.
Prior Publication US 2022/0077157 A1, Mar. 10, 2022
Int. Cl. H01L 21/00 (2006.01); H10B 12/00 (2023.01); H01L 49/02 (2006.01)
CPC H10B 12/038 (2023.02) [H01L 28/60 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for forming capacitor holes, comprising:
providing a semiconductor base in which a plurality of connecting pads are formed;
forming a supporting layer on the semiconductor base;
forming an over-etching depth adjusting layer on the supporting layer, wherein the over-etching depth adjusting layer comprises a first material layer on the supporting layer and a second material layer on the first material layer, the first material layer and the second material layer are different in materials and different from a hard mask layer formed subsequently in materials, and the first material layer and the second material layer are both thinner than the hard mask layer formed subsequently;
forming the hard mask layer on the over-etching depth adjusting layer;
etching the hard mask layer to form a plurality of etching holes, and when etching the hard mask layer to form the etching holes, over-etching the hard mask layer to reach a certain over-etching depth in the second material layer, and making the etching holes terminate in the first material layer; and
etching the first material layer and the supporting layer along the etching holes to form a plurality of capacitor holes exposing surfaces of the respective connecting pads in the supporting layer.