US 11,889,674 B2
Structure and method for SRAM FinFET device having an oxide feature
Kuo-Cheng Ching, Hsinchu County (TW); Ka-Hing Fung, Hsinchu County (TW); Chih-Sheng Chang, Hsinchu (TW); and Zhiqiang Wu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTORMANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 28, 2022, as Appl. No. 17/706,277.
Application 15/664,315 is a division of application No. 14/262,378, filed on Apr. 25, 2014, granted, now 9,721,955, issued on Aug. 1, 2017.
Application 17/706,277 is a continuation of application No. 16/913,061, filed on Jun. 26, 2020, granted, now 11,289,494.
Application 16/913,061 is a continuation of application No. 15/664,315, filed on Jul. 31, 2017, granted, now 10,700,075, issued on Jun. 30, 2020.
Prior Publication US 2022/0216222 A1, Jul. 7, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) [H01L 21/02532 (2013.01); H01L 21/0332 (2013.01); H01L 21/324 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0924 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 29/517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a substrate comprising a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer disposed over the second semiconductor layer;
forming a fin structure over the substrate, wherein the fin structure comprising a lower portion formed of the first semiconductor layer, a middle portion formed of the second semiconductor layer, and a top portion formed of the third semiconductor layer;
forming a patterned mask layer to cover a source/drain region of the fin structure while a channel region of the fin structure is exposed;
after the forming of the patterned mask layer, oxidizing the channel region of the fin structure to form a first oxide feature over sidewalls of the lower portion, a second oxide feature over sidewalls of the middle portion, and a third oxide feature over sidewalls of the top portion;
removing the first oxide feature and the third oxide feature;
depositing a first dielectric layer over the fin structure;
recessing the first dielectric layer to expose at least a portion of the top portion;
forming a dummy gate structure over the channel region;
forming a source/drain feature over the source/drain region;
depositing a second dielectric layer over the source/drain feature; and
replacing the dummy gate structure with a metal gate structure.