	US 11,889,634 B2
	Printed circuit board and method of manufacturing the same
Jung Ho Hwang, Seoul (KR); Han Su Lee, Seoul (KR); Dae Young Choi, Seoul (KR); Soon Gyu Kwon, Seoul (KR); Dong Hun Jeong, Seoul (KR); In Ho Jeong, Seoul (KR); Kil Dong Son, Seoul (KR); Sang Hwa Kim, Seoul (KR); Sang Young Lee, Seoul (KR); Jae Hoon Jeon, Seoul (KR); Jin Hak Lee, Seoul (KR); and Yun Mi Bae, Seoul (KR)
Assigned to LG INNOTEK CO., LTD., Seoul (KR)
Filed by LG INNOTEK CO., LTD., Seoul (KR)
Filed on Dec. 28, 2020, as Appl. No. 17/135,223.
Application 17/135,223 is a continuation of application No. 15/406,132, filed on Jan. 13, 2017, granted, now 10,912,202.
Application 15/406,132 is a continuation of application No. 15/241,714, filed on Aug. 19, 2016, granted, now 9,820,378, issued on Nov. 14, 2017.
Claims priority of application No. 10-2015-0116680 (KR), filed on Aug. 19, 2015.
Prior Publication US 2021/0120677 A1, Apr. 22, 2021
Int. Cl. H05K 1/11 (2006.01); H05K 3/18 (2006.01); H05K 1/02 (2006.01); H05K 1/09 (2006.01); H05K 3/10 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 3/24 (2006.01); H01L 23/00 (2006.01)

CPC H05K 3/188 (2013.01) [H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 3/002 (2013.01); H05K 3/108 (2013.01); H05K 3/184 (2013.01); H05K 3/467 (2013.01); H05K 3/4661 (2013.01); H01L 24/11 (2013.01); H01L 24/12 (2013.01); H05K 1/111 (2013.01); H05K 3/244 (2013.01); H05K 2201/0347 (2013.01); H05K 2201/098 (2013.01); H05K 2203/0548 (2013.01); H05K 2203/0588 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/1184 (2013.01); Y10T 29/49147 (2015.01)]

19 Claims

1. A circuit board comprising: an insulating layer including an upper surface and a lower surface opposite to the upper surface; a circuit layer disposed on the upper surface of the insulating layer; and a top metal layer disposed on the circuit layer, wherein the circuit layer includes a portion that is positioned higher than an upper surface of the insulating layer with respect to the lower surface of the insulating layer, wherein the top metal layer is disposed on the portion of the circuit layer, wherein the top metal layer includes a first portion, and a second portion extended outwards from the first portion, wherein the first portion is vertically overlapped with the portion of the circuit layer and is in direct physical contact with the portion of the circuit layer, wherein the second portion is not in contact with the portion of the circuit layer and does not vertically overlap with the portion of the circuit layer, wherein the top metal layer is formed of gold or a gold alloy; wherein the portion of the circuit layer includes a first layer and a second layer disposed on the first layer, wherein a thickness of the first layer is greater than a thickness of the second layer, and wherein the first layer and the second layer include a same metal material.