US 11,889,425 B2
Methods and apparatuses for mitigating reduced complexity features impact on positioning performance
Ryan Keating, Chicago, IL (US); Xiaomao Mao, Paris (FR); Nitin Mangalvedhe, Hoffman Estates, IL (US); Rapeepat Ratasuk, Inverness, IL (US); Muhammad Majid Butt, Palaiseau (FR); and Man Hung Ng, Wiltshire (GB)
Assigned to NOKIA TECHNOLOGIES OY, Espoo (FI)
Filed by NOKIA TECHNOLOGIES OY, Espoo (FI)
Filed on Sep. 10, 2021, as Appl. No. 17/471,860.
Prior Publication US 2023/0079232 A1, Mar. 16, 2023
Int. Cl. H04W 52/02 (2009.01); H04W 8/22 (2009.01); H04L 5/00 (2006.01); H04W 64/00 (2009.01)
CPC H04W 52/0261 (2013.01) [H04L 5/0051 (2013.01); H04W 8/22 (2013.01); H04W 64/003 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
at least one processor; and
at least one memory comprising computer program code,
the at least one memory and computer program code configured, with the at least one processor, to cause the apparatus at least to perform:
determining positioning performance requirements comprising both accuracy and latency of positioning according to a location management function for a positioning session;
estimating an impact of one or more reduced capability features on positioning performance based on at least measurements associated with the positioning session by considering how quickly the channel conditions are changing when determining the impact, wherein the one or more reduced capability features comprises operating in half-duplex mode;
based on the positioning performance requirements and the estimated impact, determining a subset of the one or more reduced capability features that the apparatus can implement while still achieving the positioning performance requirements for the positioning session.