US 11,889,213 B2
Sensor chip and electronic apparatus
Yohtaro Yasu, Kanagawa (JP); and Katsuhiko Hanzawa, San Jose, CA (US)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Oct. 29, 2020, as Appl. No. 17/084,170.
Application 17/084,170 is a continuation of application No. 16/469,818, granted, now 10,872,920, previously published as PCT/JP2018/030905, filed on Aug. 22, 2018.
Application 16/469,818 is a continuation of application No. 15/695,400, filed on Sep. 5, 2017, granted, now 10,418,405.
Prior Publication US 2021/0050380 A1, Feb. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/71 (2023.01); H01L 27/146 (2006.01); H04N 25/53 (2023.01); H04N 25/75 (2023.01); H04N 25/74 (2023.01); H04N 25/79 (2023.01); G01S 7/4863 (2020.01)
CPC H04N 25/745 (2023.01) [G01S 7/4863 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H04N 25/53 (2023.01); H04N 25/74 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01)] 10 Claims
OG exemplary drawing
 
1. A sensor chip comprising:
a pixel array located in a rectangular-shaped area, in which a plurality of sensor elements are arranged in an array pattern with rows and columns, the rectangular-shaped area having first and second long sides that extend in a long side direction and first and second short sides that extend in a short side direction;
a first global control circuit configured to drive the sensor elements simultaneously, the first global control circuit extending in the long side direction along the first long side, the first global control circuit comprising a first clock tree structure that includes a first plurality of buffers, and driving elements connected to the first plurality of buffers; and
a second global control circuit configured to drive the sensor elements simultaneously, the second global control circuit extending in the long side direction along the second long side, the second global control circuit comprising a second clock tree structure that includes a second plurality of buffers, and driving elements connected to the second plurality of buffers, wherein
the driving elements respectively corresponding to each column of the array pattern are connected to one of a plurality of control lines respectively disposed for each column of the sensor elements, the control lines extending in the short side direction, and the control lines respectively including a first end connected to the first global control circuit and a second end connected to the second global control circuit.