US 11,888,963 B1
Frame synch detection with rate adaptation
Claudio Rey, Chandler, AZ (US)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Jul. 28, 2022, as Appl. No. 17/876,194.
Int. Cl. H04L 7/033 (2006.01); H04L 7/00 (2006.01); H04L 7/04 (2006.01)
CPC H04L 7/0331 (2013.01) [H04L 7/0041 (2013.01); H04L 7/042 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wireless device comprising:
a receiver to wirelessly receive a packet over a channel at a first frequency and generate a sampled stream of data from the packet at a first sample rate corresponding to the first frequency;
a data resampler circuit coupled to the receiver, the data resampler circuit comprising:
a re-timer engine to determine, using a fractional conversion ratio between the first sample rate and a crystal oscillator (XO)-integer-divided sample rate, a plurality of re-timer values comprising differences between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate; and
a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values; and
a correlation circuit coupled to the data resampler circuit, the correlation circuit to use the re-sampled data values, the pseudo clock, and the plurality of re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.