CPC H04L 27/2649 (2013.01) [H04L 1/206 (2013.01); H04L 5/0055 (2013.01)] | 18 Claims |
1. An apparatus, comprising:
at least one processor; and
at least one memory including computer program code, the at least one memory and computer program code configured to, with the at least one processor, cause the apparatus at least to perform:
receiving modulated symbols over a channel comprising noise variance related to information indicating at least one of signal-to-noise ratio, estimation of channel state information, or a link quality indicator;
predicting decodability of the modulated symbols based at least upon a decodability complexity by classifying, using a machine learning model, the received modulated symbols to one class of classes indicating complexity of decoding;
determining, based on the decodability, a decoder to use for decoding the received modulated symbols; and
decoding, by the decoder, the received modulated symbols.
|