CPC H04L 25/03267 (2013.01) [H04L 25/03121 (2013.01); H04L 25/03146 (2013.01); H04L 2025/0349 (2013.01)] | 20 Claims |
1. An equalizer comprising:
an input amplifier configured to amplify and output an input signal;
a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and
a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2,
wherein the first arithmetic circuit is configured to perform weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals and output the weighted-summed received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals,
the second arithmetic circuit is configured to perform weighted summation of an output signal of the input amplifier, an output signal of the first arithmetic circuit, and the 2-1 feedback signal and output the weighted-summed output signal of the input amplifier, output signal of the first arithmetic circuit, and 2-1 feedback signal to the first sampling circuit,
the third arithmetic circuit configured to perform weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals and output the weighted-summed received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals, and
the fourth arithmetic circuit is configured to perform weighted summation of the output signal of the input amplifier, an output signal of the third arithmetic circuit, and the 1-1 feedback signal and output the weighted-summed output signal of the input amplifier, output signal of the third arithmetic circuit, and 1-1 feedback signal to the second sampling circuit.
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