US 11,888,500 B2
Encoding circuit, decoding circuit, and decoding method
Takafumi Fujimori, Tokyo (JP)
Assigned to MITSUBISHI ELECTRIC CORPORATION, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Aug. 15, 2022, as Appl. No. 17/888,059.
Application 17/888,059 is a continuation of application No. PCT/JP2020/018192, filed on Apr. 28, 2020.
Prior Publication US 2022/0393701 A1, Dec. 8, 2022
Int. Cl. H03M 13/00 (2006.01); H03M 13/13 (2006.01)
CPC H03M 13/13 (2013.01) [H03M 13/615 (2013.01); H03M 13/6575 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An encoding circuit comprising:
first polar encoding circuitry capable of encoding a polar code of a first code length;
frozen bit adding circuitry to generate a first sequence by adding frozen bits to an input signal; and
bit arrangement changing circuitry to: generate a second sequence of the first code length by arranging the first sequence in the second sequence according to an arrangement rule that depends on a ratio of a second code length and the first code length, the second code length being a code length of a polar code to be encoded and being less than or equal to the first code length, and setting bit values at bit positions other than positions where the first sequence is arranged in the second sequence to zero when the second code length is less than the first code length; and input the second sequence to the first polar encoding circuitry, wherein
a code word of the second code length is generated by thinning processing that is based on a result of encoding the second sequence by the first polar encoding circuitry.