US 11,888,498 B2
Elimination of probability of bit errors in successive approximation register (SAR) analog-to-digital converter (ADC) logic
Daniel H. Saari, Gloucester (CA); and Lewis F. Lahr, Dover, MA (US)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Jan. 18, 2022, as Appl. No. 17/578,253.
Prior Publication US 2023/0231569 A1, Jul. 20, 2023
Int. Cl. H03M 1/38 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/466 (2013.01) 19 Claims
OG exemplary drawing
 
1. A method for performing successive approximation registers (SAR) analog-to-digital conversion, the method comprising:
comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and
gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output;
wherein the digital feedback comprises an output of the next logic circuitry, the output responsive to at least one of a second positive output or a second negative output of the comparator; and
wherein:
the first positive output and the first negative output of the comparator are associated with a current bit trial; and
the at least one of the second positive output or the second negative output of the comparator are associated with a previous bit trial.