CPC H03M 1/1014 (2013.01) [G04F 10/005 (2013.01); H03L 7/085 (2013.01)] | 20 Claims |
1. A clock circuit comprising:
a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal, and configured to generate at least one digital time code; and
a calibration circuit configured to generate the time-to-digital converter calibration signal, the calibration circuit including a phase-locked loop configured to generate an error signal in response the at least one digital time code.
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