US 11,888,493 B2
Calibration of a time-to-digital converter using a virtual phase-locked loop
Timothy Adam Monk, Hudson, NH (US); Douglas F. Pastorello, Hudson, NH (US); Krishnan Balakrishnan, Austin, TX (US); and Raghunandan Kolar Ranganathan, Austin, TX (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on Dec. 16, 2022, as Appl. No. 18/083,396.
Application 18/083,396 is a continuation of application No. 17/699,350, filed on Mar. 21, 2022, granted, now 11,563,441.
Application 17/699,350 is a continuation of application No. 17/217,695, filed on Mar. 30, 2021, granted, now 11,283,459, issued on Mar. 22, 2022.
Prior Publication US 2023/0231567 A1, Jul. 20, 2023
Int. Cl. H03M 1/10 (2006.01); G04F 10/00 (2006.01); H03L 7/085 (2006.01)
CPC H03M 1/1014 (2013.01) [G04F 10/005 (2013.01); H03L 7/085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock circuit comprising:
a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal, and configured to generate at least one digital time code; and
a calibration circuit configured to generate the time-to-digital converter calibration signal, the calibration circuit including a phase-locked loop configured to generate an error signal in response the at least one digital time code.