CPC H03K 19/23 (2013.01) [G06F 7/4876 (2013.01); G06F 7/501 (2013.01); H03K 19/01742 (2013.01); H03K 19/018521 (2013.01); H03K 19/1774 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises non-linear polar material; and
a reset mechanism comprising logic to condition first terminals of capacitors of the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase, and wherein the logic comprises one or more NAND gate and NOR gates.
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