US 11,888,479 B1
Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/449,783.
Application 17/449,783 is a continuation of application No. 17/449,748, filed on Oct. 1, 2021.
Int. Cl. H03K 19/23 (2006.01); H03K 19/0185 (2006.01); G06F 7/487 (2006.01); H03K 19/017 (2006.01); G06F 7/501 (2006.01); H03K 19/17736 (2020.01)
CPC H03K 19/23 (2013.01) [G06F 7/4876 (2013.01); G06F 7/501 (2013.01); H03K 19/01742 (2013.01); H03K 19/018521 (2013.01); H03K 19/1774 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises non-linear polar material; and
a reset mechanism comprising logic to condition first terminals of capacitors of the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase, and wherein the logic comprises one or more NAND gate and NOR gates.