CPC H03K 19/018521 (2013.01) [H03K 3/037 (2013.01)] | 6 Claims |
1. An apparatus comprising:
a first latch including a first latch input, a first latch clock input, and a first latch output, the first latch input coupled to a data input, the first latch clock input coupled to a first clock input;
a first SR-Latch including a first SR-Latch input and a first SR-Latch output, the first SR-Latch input coupled to the first latch output;
a second latch including a second latch input, a second latch clock input, and a second latch output, the second latch input coupled to the data input, the second latch clock input coupled to a second clock input;
a second SR-Latch including a second SR-Latch input, the second SR-Latch input coupled to the second latch output; and
a third latch including a third latch input and a third latch clock input, the third latch input coupled to the first SR-Latch output, the third latch clock input coupled to the second clock input.
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