US 11,888,049 B2
Dielectric isolation structure for multi-gate transistors
Jen-Hong Chang, Hsinchu (TW); Yuan-Ching Peng, Hsinchu (TW); Chung-Ting Ko, Kaohsiung (TW); Kuo-Yi Chao, Hsinchu (TW); Chia-Cheng Chao, Hsinchu (TW); You-Ting Lin, Miaoli County (TW); Chih-Chung Chang, Nantou County (TW); Yi-Hsiu Liu, Hsinchu (TW); Jiun-Ming Kuo, Taipei (TW); and Sung-En Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 8, 2022, as Appl. No. 18/077,714.
Application 18/077,714 is a division of application No. 17/359,105, filed on Jun. 25, 2021, granted, now 11,532,733.
Prior Publication US 2023/0098409 A1, Mar. 30, 2023
Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first dielectric fin and a second dielectric fin;
a plurality of channel members disposed between the first dielectric fin and the second dielectric fin; and
a gate structure disposed between the first dielectric fin and the second dielectric fin and wrapping around each of the plurality of channel members,
wherein each of the first dielectric fin and the second dielectric fin comprises a base feature and a helmet feature over the base feature,
wherein the helmet feature comprises a bottom width and a top width greater than the bottom width such that the helmet feature comprises a tapered profile.