US 11,888,042 B2
Three-dimensional semiconductor memory devices and methods of fabricating the same
Kwang Soo Seol, Yongin-si (KR); Chanjin Park, Yongin-si (KR); Kihyun Hwang, Seongnam-si (KR); Hanmei Choi, Seoul (KR); Sunghoi Hur, Seoul (KR); Wansik Hwang, Hwaseong-si (KR); Toshiro Nakanishi, Seongnam-si (KR); Kwangmin Park, Seoul (KR); and Juyul Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 9, 2023, as Appl. No. 18/094,484.
Application 18/094,484 is a continuation of application No. 17/129,667, filed on Dec. 21, 2020, granted, now 11,588,032.
Application 17/129,667 is a continuation of application No. 16/859,437, filed on Apr. 27, 2020, granted, now 10,903,327, issued on Jan. 26, 2021.
Application 16/859,437 is a continuation of application No. 15/681,050, filed on Aug. 18, 2017, abandoned.
Application 15/681,050 is a continuation of application No. 14/796,569, filed on Jul. 10, 2015, granted, now 9,768,266, issued on Sep. 19, 2017.
Application 14/796,569 is a continuation of application No. 13/972,533, filed on Aug. 21, 2013, granted, now 9,564,499, issued on Feb. 7, 2017.
Application 13/972,533 is a continuation of application No. 13/072,078, filed on Mar. 25, 2011, granted, now 9,536,970, issued on Jan. 3, 2017.
Claims priority of application No. 10-2010-0027449 (KR), filed on Mar. 26, 2010; application No. 10-2010-0055098 (KR), filed on Jun. 10, 2010; application No. 10-2010-0064413 (KR), filed on Jul. 5, 2010; application No. 10-2010-0064415 (KR), filed on Jul. 5, 2010; and application No. 10-2010-0084971 (KR), filed on Aug. 31, 2010.
Prior Publication US 2023/0163182 A1, May 25, 2023
Int. Cl. H01L 27/06 (2006.01); H01L 29/423 (2006.01); H01L 21/3213 (2006.01); H10B 41/20 (2023.01); H10B 41/27 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H01L 29/792 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/42348 (2013.01) [H01L 21/32137 (2013.01); H01L 27/0688 (2013.01); H01L 29/511 (2013.01); H01L 29/517 (2013.01); H01L 29/792 (2013.01); H10B 41/20 (2023.02); H10B 41/27 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H01L 2924/0002 (2013.01)] 19 Claims
OG exemplary drawing
 
11. A semiconductor memory device comprising:
a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate;
a semiconductor pattern penetrating the stacked structure; and
a tunneling layer, a charge storage layer, a capping layer and a blocking insulation layer between the semiconductor pattern and the electrodes,
wherein each of the insulating patterns has a first sidewall adjacent the semiconductor pattern and a second sidewall opposite the first sidewall,
wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns,
wherein the capping layer comprises a silicon oxide layer,
wherein the blocking insulation layer comprises a high-k dielectric layer, and
wherein the blocking insulation layer includes a first portion extending along the second sidewalls of the insulating patterns.