CPC H01L 29/408 (2013.01) | 19 Claims |
1. An integrated circuit device, comprising:
a substrate having an active area therein;
a bit line on the substrate;
a direct contact, which extends between the active area and the bit line and electrically couples the bit line to a portion of the active area;
an electrically insulating spacer structure extending on sidewalls of the bit line and on sidewalls of the direct contact; and
a semi-insulating field passivation layer extending between the sidewalls of the direct contact and the spacer structure;
wherein the spacer structure and the field passivation layer comprise different materials; and
wherein the field passivation layer directly contacts the sidewalls of the direct contact such that a hetero-interface is defined therebetween, said hetero-interface including a quantum well, which extends within the field passivation layer and is configured to enhance a charge density within the direct contact.
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