US 11,888,008 B2
Solid-state imaging apparatus and electronic apparatus
Tetsuya Uchida, Kanagawa (JP); Ryoji Suzuki, Kanagawa (JP); Hisahiro Ansai, Kanagawa (JP); Yoichi Ueda, Kanagawa (JP); Shinichi Yoshida, Kanagawa (JP); Yukari Takeya, Kanagawa (JP); Tomoyuki Hirano, Kanagawa (JP); Hiroyuki Mori, Kanagawa (JP); Hirotoshi Nomura, Kanagawa (JP); Yoshiharu Kudoh, Kanagawa (JP); Masashi Ohura, Tokyo (JP); and Shin Iwabuchi, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Sep. 29, 2021, as Appl. No. 17/489,427.
Application 17/489,427 is a continuation of application No. 16/486,664, granted, now 11,171,167, previously published as PCT/JP2018/006415, filed on Feb. 22, 2018.
Claims priority of application No. 2017-043810 (JP), filed on Mar. 8, 2017.
Prior Publication US 2022/0020799 A1, Jan. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14623 (2013.01) [H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14614 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01); H01L 27/14683 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a substrate;
a plurality of photoelectric conversion elements in the substrate, wherein each of the plurality of photoelectric conversion elements includes an N-type region that performs photoelectric conversion;
a light-shielding wall between a first photoelectric conversion element and a second photoelectric conversion element of the plurality of photoelectric conversion elements in the substrate in a cross-sectional view;
a first P-type region between the first photoelectric conversion element and the light-shielding wall in the cross-sectional view;
a second P-type region adjacent to the first P-type region and between the first photoelectric conversion element and a light incident side of the substrate in the cross-sectional view; and
a vertical-type transistor extending in a depth direction of the substrate in the cross-sectional view, wherein a gate of the vertical-type transistor includes two trench-type electrodes.