CPC H01L 27/1203 (2013.01) [H01L 21/84 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 27/13 (2013.01); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01)] | 10 Claims |
1. A semiconductor memory device, comprising:
an interlayer insulating layer;
an active pattern on the interlayer insulating layer;
a first word line and a second word line on the interlayer insulating layer and crossing the active pattern, the first word line and the second word line enclosing a side surface of the active pattern and a top surface of the active pattern, and the first word line and the second word line extending in a first direction;
a first capacitor connected to a first end portion of the active pattern;
a second capacitor connected to a second end portion of the active pattern;
a bit line contact plug connected to the active pattern, the bit line contact plug being between the first word line and the second word line; and
a bit line connected to the bit line contact plug, the bit line extending in a second direction and crossing the first word line and the second word line.
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