US 11,887,986 B2
Semiconductor memory device
Sungwon Yoo, Hwaseong-si (KR); Yongseok Kim, Suwon-si (KR); Ilgweon Kim, Hwaseong-si (KR); Hyuncheol Kim, Seoul (KR); Hyeoungwon Seo, Yongin-si (KR); Kyunghwan Lee, Seoul (KR); and Jaeho Hong, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 18, 2021, as Appl. No. 17/503,713.
Claims priority of application No. 10-2021-0000269 (KR), filed on Jan. 4, 2021.
Prior Publication US 2022/0216239 A1, Jul. 7, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 25/065 (2023.01); H01L 21/84 (2006.01); H01L 27/13 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/84 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 27/13 (2013.01); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
an interlayer insulating layer;
an active pattern on the interlayer insulating layer;
a first word line and a second word line on the interlayer insulating layer and crossing the active pattern, the first word line and the second word line enclosing a side surface of the active pattern and a top surface of the active pattern, and the first word line and the second word line extending in a first direction;
a first capacitor connected to a first end portion of the active pattern;
a second capacitor connected to a second end portion of the active pattern;
a bit line contact plug connected to the active pattern, the bit line contact plug being between the first word line and the second word line; and
a bit line connected to the bit line contact plug, the bit line extending in a second direction and crossing the first word line and the second word line.