US 11,887,984 B2
Complementary transistor and semiconductor device
Hidetoshi Oishi, Saga (JP); Koichi Matsumoto, Kanagawa (JP); and Kazuyuki Tomida, Kanagawa (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Apr. 7, 2021, as Appl. No. 17/224,617.
Application 17/224,617 is a continuation of application No. 16/893,280, filed on Jun. 4, 2020, granted, now 11,004,851.
Application 16/893,280 is a continuation of application No. 16/316,702, granted, now 10,720,432, issued on Jul. 21, 2020, previously published as PCT/JP2017/023165, filed on Jun. 23, 2017.
Claims priority of application No. 2016-142699 (JP), filed on Jul. 20, 2016; and application No. 2017-118682 (JP), filed on Jun. 16, 2017.
Prior Publication US 2021/0225841 A1, Jul. 22, 2021
Int. Cl. H01L 27/092 (2006.01); H01L 29/778 (2006.01); H01L 29/786 (2006.01); H01L 29/16 (2006.01); H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 29/267 (2006.01); H01L 29/24 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H10B 10/00 (2023.01); H01L 21/265 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/26506 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/16 (2013.01); H01L 29/1606 (2013.01); H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/41791 (2013.01); H01L 29/4232 (2013.01); H01L 29/66045 (2013.01); H01L 29/66795 (2013.01); H01L 29/7391 (2013.01); H01L 29/778 (2013.01); H01L 29/7851 (2013.01); H01L 29/78618 (2013.01); H01L 29/78639 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H10B 10/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A complementary transistor, comprising:
a semiconductor substrate;
a first transistor including:
a first control electrode;
a first active region located below the first control electrode;
a first A extension region extending from one end of the first active region;
a first B extension region extending from the other end of the first active region; and
a buffer layer provided between the first control electrode and the semiconductor substrate; and
a second transistor including:
a second control electrode;
a second active region located below the second control electrode;
a second A extension region extending from one end of the second active region; and
a second B extension region extending from the other end of the second active region.