US 11,887,976 B2
Land-side silicon capacitor design and semiconductor package using the same
Che-Hung Kuo, Hsinchu (TW); and Yi-Jyun Lee, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsin-Chu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Oct. 6, 2021, as Appl. No. 17/494,851.
Claims priority of provisional application 63/105,379, filed on Oct. 26, 2020.
Prior Publication US 2022/0130814 A1, Apr. 28, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 27/01 (2006.01); H01L 25/065 (2023.01); H01L 23/58 (2006.01); H01L 49/02 (2006.01)
CPC H01L 27/01 (2013.01) [H01L 25/0657 (2013.01); H01L 23/49816 (2013.01); H01L 23/585 (2013.01); H01L 28/40 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06572 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a semiconductor die mounted on a top surface of the package substrate;
a plurality of conductive elements disposed on a bottom surface of the package substrate; and
a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements, wherein the land-side silicon capacitor comprises at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region, wherein the land-side silicon capacitor is surrounded by an annular, ring-shaped arrangement of conductive terminals comprising a first half-ring of ground conductive terminals arranged in proximity to anode terminals of the at least two silicon capacitor unit dies and a second half-ring of power conductive terminals arranged in proximity to cathode terminals of the at least two silicon capacitor unit dies.