	US 11,887,957 B2
	Semiconductor device
Jubin Seo, Seongnam-si (KR); Sujeong Park, Hwaseong-si (KR); Kwangjin Moon, Hwaseong-si (KR); and Myungjoo Park, Pohang-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 7, 2022, as Appl. No. 18/076,529.
Application 18/076,529 is a continuation of application No. 17/108,140, filed on Dec. 1, 2020, granted, now 11,538,782.
Claims priority of application No. 10-2020-0043334 (KR), filed on Apr. 9, 2020.
Prior Publication US 2023/0108516 A1, Apr. 6, 2023
Int. Cl. H01L 23/00 (2006.01)

CPC H01L 24/13 (2013.01) [H01L 24/05 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05001 (2013.01); H01L 2224/13099 (2013.01); H01L 2924/014 (2013.01); H01L 2924/3651 (2013.01)]

20 Claims

1. A method of manufacturing semiconductor device, the method comprising:

forming an under-bump pattern and a protective layer on a semiconductor substrate;

forming a seed layer on the under-bump pattern and the protective layer;

forming a resist pattern comprising a guide opening on the seed layer, the guide opening exposing at least a portion of a top surface of the seed layer which overlaps the under-bump pattern;

forming a preliminary bump pattern in the guide opening of the resist pattern; and

performing an annealing process to the preliminary bump pattern.