US 11,887,934 B2
Package structure and fabrication methods
Han-Wen Chen, Cupertino, CA (US); Steven Verhaverbeke, San Francisco, CA (US); Giback Park, San Jose, CA (US); Giorgio Cellere, Torri di Quartesolo (IT); Diego Tonini, Treviso (IT); Vincent DiCaprio, Pleasanton, CA (US); and Kyuil Cho, Santa Clara, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Dec. 5, 2022, as Appl. No. 18/075,141.
Application 18/075,141 is a continuation of application No. 17/227,811, filed on Apr. 12, 2021, granted, now 11,521,935.
Application 17/227,811 is a continuation of application No. 16/687,567, filed on Nov. 18, 2019, granted, now 11,264,331, issued on Mar. 1, 2022.
Claims priority of application No. 102019000006736 (IT), filed on May 10, 2019.
Prior Publication US 2023/0187370 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/66 (2006.01); H01Q 1/22 (2006.01); H01Q 1/24 (2006.01); H05K 1/02 (2006.01); H01L 21/50 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01); H01L 21/60 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/486 (2013.01); H01L 21/4864 (2013.01); H01L 21/50 (2013.01); H01L 21/76802 (2013.01); H01L 23/13 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 23/49894 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/66 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 27/0688 (2013.01); H01Q 1/2283 (2013.01); H01Q 1/243 (2013.01); H05K 1/0243 (2013.01); H01L 2021/60007 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1035 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a frame, comprising:
a patterned substrate comprising a semiconductor material, the patterned substrate having a first side opposite a second side;
a first opening formed in the patterned substrate and extending from the first side to the second side; and
a plurality of second openings formed in the patterned substrate along an edge of the first opening and extending from the first side to the second side, each of the plurality of second openings having a first lateral dimension adjacent the first side and a second lateral dimension adjacent the second side, wherein a morphology of the plurality of second openings is different from a morphology of the first opening;
a semiconductor device disposed within the first opening;
a metallic interconnection disposed within at least one of the plurality of second openings and extending at least between the first side and the second side;
a dielectric material disposed over the first side and the second side and within the first opening and each of the plurality of second openings, the dielectric material disposed over each side of the semiconductor device and between the metallic interconnection and a sidewall of the at least one of the plurality of second openings; and
an intermediate layer disposed between the dielectric material and the metallic interconnection within the at least one of the plurality of second openings.