US 11,887,924 B2
Chip scale package
Craig McAdam, Edinburgh (GB); Jonathan Taylor, London (GB); Douglas Macfarlane, Edinburgh (GB); John Kerr, Edinburgh (GB); James Munger, Austin, TX (US); John Pavelka, Austin, TX (US); and Steven A. Atherton, Austin, TX (US)
Assigned to Cirrus Logic Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on Nov. 23, 2022, as Appl. No. 17/993,638.
Application 17/993,638 is a continuation of application No. 17/245,259, filed on Apr. 30, 2021, granted, now 11,562,952.
Claims priority of provisional application 63/143,233, filed on Jan. 29, 2021.
Prior Publication US 2023/0088252 A1, Mar. 23, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 23/49822 (2013.01); H01L 24/13 (2013.01); H01L 2224/16227 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A chip scale package (CSP) comprising:
a semiconductor die;
a first set of CSP contact balls or bumps comprising a discontinuous first ring or loop of CSP contact balls or bumps;
a second set of CSP contact balls or bumps, wherein the first and second sets of CSP contact balls or bumps are coupled to the semiconductor die and are positioned within a perimeter of the semiconductor die; and
a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps;
wherein the first and second sets of CSP contact balls or bumps are configured for directly mounting the CSP on, and electrically coupling the CSP to, a substrate of a host device incorporating the CSP, and the CSP is approximately the same size as the semiconductor die; and
wherein the channel routing region is provided, at least in part, by a discontinuity in the first ring or loop.