	US 11,887,892 B2
	Method for forming semiconductor die with die region and seal-ring region
Jin Won Jeong, Seoul (KR); Jang Hee Lee, Cheongju-si (KR); Young Hun Jun, Cheongju-si (KR); Jong Woon Lee, Cheongju-si (KR); and Jae Sik Choi, Cheongju-si (KR)
Assigned to MagnaChip Semiconductor, Ltd., Cheongju-si (KR)
Filed by MagnaChip Semiconductor, Ltd., Cheongju-si (KR)
Filed on Apr. 15, 2021, as Appl. No. 17/231,214.
Claims priority of application No. 10-2020-0082705 (KR), filed on Jul. 6, 2020.
Prior Publication US 2022/0005733 A1, Jan. 6, 2022
Int. Cl. H01L 21/78 (2006.01); H01L 21/66 (2006.01); H01L 21/56 (2006.01); H01L 23/10 (2006.01); H01L 23/31 (2006.01)

CPC H01L 21/78 (2013.01) [H01L 21/56 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01); H01L 23/10 (2013.01); H01L 23/3171 (2013.01)]

19 Claims

1. A method for forming a semiconductor die, the method comprising:

forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region;

forming a metal pad and a test pad on the interlayer dielectric layer;

forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad;

first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process;

second etching the passivation dielectric layer to expose the metal pad and the test pad;

forming a bump on the metal pad; and

dicing the substrate while removing the scribe line region by mechanical sawing.