US 11,887,891 B2
Self-aligned contacts
Mark T. Bohr, Aloha, OR (US); Tahir Ghani, Portland, OR (US); Nadia M. Rahhal-Orabi, Lake Oswego, OR (US); Subhash M. Joshi, Hillsboro, OR (US); Joseph M. Steigerwald, Forest Grove, OR (US); Jason W. Klaus, Portland, OR (US); Jack Hwang, Portland, OR (US); and Ryan Mackiewicz, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 17, 2023, as Appl. No. 18/098,029.
Application 13/786,372 is a division of application No. 12/655,408, filed on Dec. 30, 2009, granted, now 8,436,404, issued on May 7, 2013.
Application 18/098,029 is a continuation of application No. 17/147,423, filed on Jan. 12, 2021, granted, now 11,600,524.
Application 17/147,423 is a continuation of application No. 16/819,590, filed on Mar. 16, 2020, granted, now 10,930,557, issued on Feb. 23, 2021.
Application 16/819,590 is a continuation of application No. 16/162,186, filed on Oct. 16, 2018, granted, now 10,629,483, issued on Apr. 21, 2020.
Application 16/162,186 is a continuation of application No. 15/827,491, filed on Nov. 30, 2017, granted, now 10,141,226, issued on Nov. 27, 2018.
Application 15/827,491 is a continuation of application No. 15/299,106, filed on Oct. 20, 2016, granted, now 9,892,967, issued on Feb. 13, 2018.
Application 15/299,106 is a continuation of application No. 14/998,092, filed on Dec. 23, 2015, granted, now 9,508,821, issued on Nov. 29, 2016.
Application 14/998,092 is a continuation of application No. 14/731,363, filed on Jun. 4, 2015, granted, now 9,466,565, issued on Oct. 11, 2016.
Application 14/731,363 is a continuation of application No. 14/174,822, filed on Feb. 6, 2014, granted, now 9,054,178, issued on Jun. 9, 2015.
Application 14/174,822 is a continuation of application No. 13/786,372, filed on Mar. 5, 2013, granted, now 9,093,513, issued on Jul. 28, 2015.
Prior Publication US 2023/0154793 A1, May 18, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/283 (2013.01); H01L 21/28123 (2013.01); H01L 21/28229 (2013.01); H01L 21/28255 (2013.01); H01L 21/28562 (2013.01); H01L 21/31105 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/42364 (2013.01); H01L 29/456 (2013.01); H01L 29/4966 (2013.01); H01L 29/512 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66477 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01); H01L 29/785 (2013.01); H01L 29/495 (2013.01); H01L 2029/7858 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a substrate comprising silicon;
a first structure above the substrate, the first structure comprising a first gate dielectric and a first gate electrode;
a first spacer adjacent to a first side of the first structure;
a second spacer adjacent to a second side of the first structure;
a second structure above the substrate, the second structure comprising a second gate dielectric and a second gate electrode;
a third spacer adjacent to a first side of the second structure;
a fourth spacer adjacent to a second side of the second structure;
a source or drain region between the second spacer and the third spacer;
a trench contact on the source or drain region;
a first inter-layer dielectric (ILD) layer directly on and vertically over the first spacer, the first structure, the second spacer, the third spacer, the second structure, and the fourth spacer, wherein the first ILD layer has a first opening vertically over the source or drain region, and wherein the first ILD layer is a planar ILD layer; and
a second ILD layer on the first ILD layer, wherein the second ILD layer has a second opening vertically over the first opening.