US 11,887,889 B2
Semiconductor device and method for manufacturing the same
Zheng Lv, Hangzhou (CN); Xunyi Song, Hangzhou (CN); and Meng Wang, Hangzhou (CN)
Assigned to Silergy Semiconductor Technology (Hangzhou) LTD, Hangzhou (CN)
Filed by Silergy Semiconductor Technology (Hangzhou) LTD, Hangzhou (CN)
Filed on Jun. 2, 2021, as Appl. No. 17/336,539.
Claims priority of application No. 202010510070.7 (CN), filed on Jun. 8, 2020.
Prior Publication US 2021/0384073 A1, Dec. 9, 2021
Int. Cl. H01L 21/768 (2006.01)
CPC H01L 21/76877 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a) a lower metal layer having a first region and a second region that are isolated from each other;
b) an interlayer dielectric layer located on an upper surface of the lower metal layer;
c) a through hole extending from an upper surface of the interlayer dielectric layer to the lower metal layer to expose the upper surface of the lower metal layer;
d) a first conductive layer covering a bottom part and sidewall parts of the through hole, and the upper surface of the interlayer dielectric layer;
e) a first dielectric layer covering the first conductive layer above the first region of the lower metal layer;
f) a first metal filling the through hole; and
g) an upper metal layer located above the upper surface of the interlayer dielectric layer, wherein above the first region of the lower metal layer, the upper metal layer is in contact with the first metal and the first dielectric layer.