US 11,887,691 B2
Temporal memory systems and methods
Advait Madhavan, Bethesda, MD (US)
Assigned to UNIVERSITY OF MARYLAND, COLLEGE PARK, College Park, MD (US)
Filed by University of Maryland, College Park, College Park, MD (US)
Filed on Oct. 1, 2021, as Appl. No. 17/492,524.
Claims priority of provisional application 63/086,453, filed on Oct. 1, 2020.
Prior Publication US 2022/0108735 A1, Apr. 7, 2022
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01); H03K 19/20 (2006.01); G11C 7/12 (2006.01); G06F 17/16 (2006.01); G11C 5/06 (2006.01)
CPC G11C 7/222 (2013.01) [G06F 17/16 (2013.01); G11C 5/06 (2013.01); G11C 7/1012 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); H03K 19/20 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A temporal memory comprising:
a group of tunable delay components in electrical communication with a set of input lines and a set of output lines;
a write circuit connected to the tunable delay components such that an electrical signal can be controllably applied to each of the tunable delay components in correspondence with relative timing of a set of arriving wavefronts at the input lines associated with the tunable delay components, wherein the set of arriving wavefronts temporally encode data in their relative delay; and
a read circuit connected to the tunable delay components such that an output signal can be controllably conducted through the tunable delay components so as to cause a set of memory recall wavefronts to be generated at the set of output lines having a relative delay corresponding to the relative delay of the set of arriving wavefronts.