US 11,887,689 B2
Techniques for precharging a memory cell
Ferdinando Bedeschi, Biassono (IT); and Umberto Di Vincenzo, Capriate San Gervasio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 26, 2022, as Appl. No. 17/585,307.
Application 17/585,307 is a division of application No. 16/512,999, filed on Jul. 16, 2019, granted, now 11,238,907.
Application 16/512,999 is a division of application No. 15/857,091, filed on Dec. 28, 2017, granted, now 10,403,336, issued on Sep. 3, 2019.
Prior Publication US 2022/0223187 A1, Jul. 14, 2022
Int. Cl. G11C 7/12 (2006.01); G11C 11/22 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2273 (2013.01); G11C 11/2293 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a word line coupled with a memory cell that is configured to store a logic state;
a sense component comprising:
a capacitor coupled with a digit line associated with the memory cell and configured to discharge to a voltage representative of the logic state during a period of time that the word line is activated; and
a switching component coupled with the digit line, wherein the sense component is configured to activate the switching component after the capacitor discharges to the voltage representative of the logic state to transfer charge to the digit line from the capacitor to discharge the capacitor to a reference voltage during the period of time that the word line is activated.