US 11,887,682 B2
Anti-fuse memory cell circuit, array circuit and reading and writing method thereof
Xin Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/432,808
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed Feb. 22, 2020, PCT No. PCT/CN2020/076311
§ 371(c)(1), (2) Date Aug. 20, 2021,
PCT Pub. No. WO2021/056958, PCT Pub. Date Apr. 1, 2021.
Claims priority of application No. 201910931356 (CN), filed on Sep. 29, 2019.
Prior Publication US 2022/0122680 A1, Apr. 21, 2022
Int. Cl. G11C 17/16 (2006.01); G11C 17/06 (2006.01); G11C 17/18 (2006.01)
CPC G11C 17/06 (2013.01) [G11C 17/18 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An anti-fuse memory cell circuit, comprising:
an anti-fuse device;
a switch module, coupled to the anti-fuse device;
a selection module, coupled to the switch module; and
a control module, respectively coupled to the anti-fuse device and the switch module;
wherein, the control module is configured to switch an on-off mode of the switch module according to a breakdown state of the anti-fuse device;
wherein the anti-fuse device has a first end and a second end,
wherein the switch module includes a first switch unit and a second switch unit, wherein each of the first switch unit and the second switch unit has a first terminal, a second terminal and a control terminal, wherein the control terminal is coupled to the control module; and
wherein the second terminals of the first and the second switch units are each coupled to the selection module, wherein the first terminal of the first switch unit is coupled to the first end of the anti-fuse device, and wherein the first terminal of the second switch unit is coupled to the second end of the anti-fuse device.