US 11,887,681 B2
Performing selective copyback in memory devices
Vamsi Rayaprolu, San Jose, CA (US); Ashutosh Malshe, Fremont, CA (US); Gary Besinga, Boise, ID (US); and Roy Leonard, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 18, 2022, as Appl. No. 17/675,477.
Prior Publication US 2023/0268018 A1, Aug. 24, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); G11C 16/26 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/3495 (2013.01) [G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
determining a data validity metric value with respect to a source set of memory cells of the memory device;
determining whether the data validity metric value satisfies a first threshold criterion;
responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value;
determining whether the data integrity metric value satisfies a second threshold criterion; and
responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.