US 11,887,680 B2
Reducing program verifies for multi-level NAND cells
Jeffrey S. McNeil, Nampa, ID (US); Jason Lee Nevill, Boise, ID (US); and Tommaso Vali, Sezze (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 26, 2022, as Appl. No. 17/873,716.
Application 17/873,716 is a continuation of application No. 16/907,594, filed on Jun. 22, 2020, granted, now 11,417,406.
Prior Publication US 2022/0359025 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 2211/5621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a multi-level cell (MLC) memory array, each MLC of the MLC memory array being programmable to a plurality of levels including a first level and a second level; and
a memory controller coupled to the MLC memory array and configured to perform programming operations on the MLC memory array, comprising:
applying, at a first time, a single-valued first programming voltage to a first group of memory cells of the MLC memory array;
performing a first verify operation to determine a first programming effectiveness metric comprising a first amount of the first group of memory cells that were successfully programmed to the first level in response to the first programming voltage at the first time; and
based on the first programming effectiveness metric and a predetermined threshold, determining whether to perform a second verify operation to determine a second programming effectiveness metric comprising a second amount of the first group of memory cells that were successfully programmed to the second level by the first programming voltage at the first time.