CPC G11C 16/3459 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 2211/5621 (2013.01)] | 20 Claims |
1. A system comprising:
a multi-level cell (MLC) memory array, each MLC of the MLC memory array being programmable to a plurality of levels including a first level and a second level; and
a memory controller coupled to the MLC memory array and configured to perform programming operations on the MLC memory array, comprising:
applying, at a first time, a single-valued first programming voltage to a first group of memory cells of the MLC memory array;
performing a first verify operation to determine a first programming effectiveness metric comprising a first amount of the first group of memory cells that were successfully programmed to the first level in response to the first programming voltage at the first time; and
based on the first programming effectiveness metric and a predetermined threshold, determining whether to perform a second verify operation to determine a second programming effectiveness metric comprising a second amount of the first group of memory cells that were successfully programmed to the second level by the first programming voltage at the first time.
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