US 11,887,674 B2
Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction
Yanjie Wang, San Jose, CA (US); Guirong Liang, Cupertino, CA (US); Xiaoyu Che, San Jose, CA (US); and Yi Song, San Jose, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Mar. 29, 2022, as Appl. No. 17/706,993.
Prior Publication US 2023/0317174 A1, Oct. 5, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/24 (2006.01); G11C 16/32 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in strings coupled to one of a plurality of bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the plurality of bit lines and configured to:
read each of the memory cells in a read operation, and
for each one of the memory cells, offset at least one of a bit line settling time and a kick voltage applied to the one of the plurality of bit lines coupled to the one of the memory cells during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.