CPC G11C 16/16 (2013.01) [G11C 7/1039 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01)] | 20 Claims |
1. A nonvolatile memory device comprising:
a plurality of bit lines connected with a plurality of cell strings;
a common source line connected with the plurality of cell strings;
at least one dummy bit line provided between the common source line and the plurality of bit lines;
a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device; and
a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal, wherein the dummy bit line driver includes:
a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage and configured to operate in response to a first dummy bit line driving signal of the at least one dummy bit line driving signal; and
a second switch connected between the at least one dummy bit line and the common source line and configured to operate in response to a second dummy bit line driving signal of the at least one dummy bit line driving signal.
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